1. Field of the Invention
This invention relates generally to semiconductor fabrication processes, and more particularly to fabrication processes used in the manufacture of smart cards.
2. Description of the Prior Art
The primary failure mode of existing smart cards is semiconductor die breakage resulting from applied mechanical stress. Unfortunately, mechanical stress is inherent in typical smart card operational environments, such as point-of-sale terminals, credit card reading devices, wallets, pockets, and purses. Semiconductor die strength is a significant factor in determining the overall durability and reliability of a smart card. Die thickness directly affects the ability of a semiconductor die to withstand flexure and applied mechanical force.
Existing smart card packages are approximately 0.030 inches thick. This dimension places constraints on the maximum allowable thickness of the semiconductor die which will fit within the package. In addition to the die itself, space must also be allocated for lead termination, protection, labeling, magnetic striping, and discrete circuit components. Therefore, die thicknesses on the order of 0.011 inches are employed, representing the maximum die thickness that can easily fit within a smart card package. Semiconductor die thinner than 0.011 inches are not generally used in smart cards, as such die have traditionally been difficult and expensive to fabricate. Furthermore, conventional wisdom dictates that, as the thickness of a die is decreased, the die become increasingly vulnerable to mechanical failure. For all of the aforementioned reasons, existing smart card design approaches have not advantageously exploited the use of die thinner than 0.011 inches.
One shortcoming of existing 0.011-inch die is that the die do not provide optimum immunity to mechanical flexure. Flexure is an important physical property to consider for certain specific applications such as smart cards. In order to improve performance in this area, existing approaches have focused on strengthening the die itself, generally through the optimization of specific individual design parameters, such as grinding parameters, dicing parameters, and others. As opposed to integrating these design parameters into a broad-based design solution, prior art approaches have generally adopted a piecemeal approach by considering the effects of only one or two design parameters on flexure resistance. In material systems having high thermal coefficients of expansion, design parameters have been optimized for the purpose of increasing die tolerance to severe thermal transient conditions. However, existing die strength improvement efforts have not adequately addressed applications involving physical die flexure.
Existing chemical stress relief processes have not been directed towards the goal of improving die strength. Rather, these stress relief processes are used to remove silicon and thin silicon wafers, flatten wafers that are warped, and repair damage caused by wafer grinding. Wafers are typically subjected to mechanical thinning operations for purposes of processing and testing. Mechanical thinning places stress concentrations on the wafers, resulting in the aforementioned wafer warpage, which is corrected using chemical methods such as acid baths. The purpose of existing chemical stress relief processes is to repair wafer damage which may occur during wafer fabrication and processing.
It would be desirable to develop a chemical stress relief process which is directed to improving die strength. Although a pure crystal of silicon has an inherent maximum strength, the strength of a crystal fabricated in conformance with state-of-the-art technology is compromised by the existence of crystallographic defects such as chips, scratches, inclusions, and lattice dislocations. Chipping may result during the dicing and/or die handling process. Prevention or removal of these defects will enhance the actual strength of the crystal. For example, existing semiconductor integrated circuits typically have greater resistance to mechanical stress which is applied at the front or side of the circuit, as opposed to the back of the circuit. This phenomenon is due to crystallographic defects introduced in the fabrication process. Accordingly, it would be desirable to develop a chemical etching or dissolution process to eliminate the stress concentration and crack initiation points in the crystal lattice structure.
Traditional smart card packaging techniques place the semiconductor die near the surface of the card, due to tight packaging and interconnect requirements, and also because the thickness of the die represents a substantial portion of the thickness of the actual smart card package. However, during mechanical flexure, the mechanical stresses are greatest near the card surface, and at a minimum value on the neutral axis of the card, i.e., at a depth equal to half the card thickness. Since the stresses are low or zero at this axis, it would be desirable to position the semiconductor die at this location. However, even if an existing 0.011 inch die is centered on the neutral axis, the sheer thickness of the die itself results in portions of the die being located in higher stress regions near the surface of the card. What is needed is a thinner die, such that the entire die can be situated at or near the neutral axis.